The present invention relates generally to electronics and, more particularly, to analog-to-digital converters (ADCs).
An ADC receives an analog input signal and generates a digital output signal that represents the magnitude of the analog input signal. Over-sampled Delta-Sigma ADCs and Nyquist (like flash, cyclic, SAR, etc.) ADCs are two known types of ADC. Also known are two-step, hybrid ADCs that use a Delta-Sigma conversion for one or more most significant bits (MSBs) in a first conversion step and then Nyquist conversion for one or more least significant bits (LSBs) in a second conversion step, where the MSBs and LSBs are then combined to generate the digital output signal. Because the Delta-Sigma conversion is typically oversampled, it takes longer (more clock cycles) to resolve each bit than with Nyquist conversion, which resolves each bit in a single cycle. Using Nyquist conversion to resolve the LSBs in a hybrid ADC speeds up the overall ADC conversion process compared to a Delta-Sigma ADC.
ADCs are known to experience offset and flicker noise that can adversely affect the accuracy of the output signal generated by the ADC. One technique for reducing the effects of offset and flicker noise in ADCs is chopping. Chopping relies on up-conversion of offset and flicker noise in the frequency domain and subsequent low-pass filtering. In a two-step, hybrid ADC, it is known to apply chopping both in the Delta-Sigma portion that generates the MSBs and in the Nyquist portion that generates LSBs.
However, in a two-step hybrid incremental Delta-Sigma ADC, it also is necessary to scale the reference for the second conversion step. Inaccuracy in this scaling can result in non-linearity, so chopping is not effective in removing the offset during the second conversion step because there is no effective filtering mechanism for offset, which has been up-converted to the chopping frequency. Accordingly, it would be advantageous to have two-step Delta-Sigma ADC that performs accurate scaling.